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JOB DESCRIPTION: Experienced ASIC verification engineer that can take ownership of verification environment, develop new verification IP components in system verilog. Responsibilities include, developing of verification plan, verification IP module specs, writing system verilog3/31/2013 San Jose, CA Save This Job
Relevant Experience: 3+ years? experience in ASIC Verification Location: Raleigh, North Carolina Description: This position will be part of a small, fast-paced Verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of5/24/2013 Milpitas, CA Save This Job
Reporting to: Verification Manager, VLSI Engineering Location: Irvine, CA or Los Altos, CA Job Description The Design Verification team is growing and has need of a top talent, senior to principal level, ASIC functional verification engineer. Responsible for the development4/21/2013 Irvine, CA Save This Job
Candidate will be responsible for high speed ASIC design and verification for Network controller type ASICs. 10+ experience in the ASIC and design and verification methodology, with some experience in emulation platforms is a plus. Candidate must have working experience of OVM3/23/2013 Irvine, CA Save This Job
Description: We are seeking a sharp and highly motivated person whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. Candidate will work closely with our industry experienced physical design and/or logical design ASIC team developing4/16/2013 Santa Clara Save This Job
Candidate must have 3 to 5 years experience in simulation / verification of complex designs in verilog / system verilog. Experience in gate level timing simulation and DFT related experience is a plus. Qualifications: Thorough understanding of verilog constructs and4/16/2013 Santa Clara, CA Save This Job
Job Duties: Write programs to verify video processing/encoding/decoding digital integrated circuits. Develop software for system tests on FPGA-based emulation systems. Full time. Requirements: Req. MS in Comp. Sys. Engineering, CS, or EE, proficiency in SystemVerilog, and FPGA5/9/2013 Andover, MA Save This Job
Job Description The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can include vector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs.4/21/2013 Irvine, CA Save This Job
We are looking for ASIC design engineers to create industry leading next generation high speed network controller ASIC products. Responsibilities: Micro-architecture and RTL coding based on architecture specification Generate synthesis and timing signoff constraints3/23/2013 Irvine, CA Save This Job
uThe role involves ASIC and FPGA verification including contributing to verification methodology, developing test plans that ensures high coverage between random, directed and in-system environments, system infrastructure development and debug, with significant focus on testing5/9/2013 Sunnyvale, CA Save This Job
SeaMicro is looking for an experienced Senior ASIC Designer to architect and implement SeaMicro super-compute style fabric device for its next generation data center products. This is an excellent opportunity for high-energy candidates who can take a product from conception,4/9/2013 Santa Clara, CA Save This Job
JOB DESCRIPTION: Experienced ASIC designer to design and develop digital components of wireless and display SOCs. Responsibilities include chip design / specification, FPGA prototyping, RTL coding, RTL verification, board bring up, and software integration/testing. The position3/31/2013 San Jose, CA Save This Job
Tracking Code 511 Job Description Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. It is growing to also offer IP subsystems in application domains such as Baseband and Imaging. As a member of the DSP engineering group4/24/2013 Santa Clara, CA Save This Job
Job Description Your goal is to formulate and validate the next generation ASIC architecture for an audio noise suppression market leading product. You will work closely with VLSI Architecture, Design, Verification and DSP teams. Scope of responsibility will include proposing,3/23/2013 Mountain View, CA Save This Job
Required Skill and Experience: MS/Ph.D. in Electrical Engineering with 5 years of ASIC design experience. A strong background in ASIC design process and development, Verilog, Synthesis, place and route, and verification. Previous management experience is3/19/2013 San Jose, CA Save This Job
SeaMicro is looking for an experienced Senior Chip Integration Engineer to drive the physical implementation of our next generation super-compute style fabric ASIC. This is an excellent opportunity for high-energy candidates with strong technical leadership skills to take a chip4/9/2013 Santa Clara, CA Save This Job
We are looking for a FPGA Design Engineer to be involved in a variety of projects. This position will require a good understanding in FPGA development from concept / architecture level to final implementation and verification of final design.Responsibilities:Full FGPA design5/1/2013 Santa Clara, CA Save This Job
Job Details Responsibility is to design the next generation chips for audio noise suppression. This engineer would be responsible for Timing and physical design of our SoCs. Would involve close interactions with the VLSI Architecture, Design, Verification and Implementation3/23/2013 Mountain View, CA Save This Job
Job Description / Responsibilities will include the following: 1. Acquire new and advanced formal concepts and apply advanced engineering methodologies to solve customer verification problems 2. Provide pre and post sales support, including working closely with account4/21/2013 Mountain View, CA Save This Job
Calxeda is headquartered in Austin, Texas. Our company mission is to bring revolutionary computational efficiency to the data center built around the ultra-low-power ARM architecture. Furthermore, we are developing server platform technologies that scale efficiently to thousands5/10/2013 Austin, TX Save This Job