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Candidate must have 3 to 5 years experience in simulation / verification of complex designs in verilog / system verilog. Experience in gate level timing simulation and DFT related experience is a plus. Qualifications: Thorough understanding of verilog constructs and
4/16/2013 Santa Clara, CA Save This JobJob Description The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can include vector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs.
3/12/2013 Irvine, CA Save This JobJob Description Your goal is to formulate and validate the next generation ASIC architecture for an audio noise suppression market leading product. You will work closely with VLSI Architecture, Design, Verification and DSP teams. Scope of responsibility will include proposing,
3/23/2013 Mountain View, CA Save This JobWe are looking for ASIC design engineers to create industry leading next generation high speed network controller ASIC products. Responsibilities: Micro-architecture and RTL coding based on architecture specification Generate synthesis and timing signoff constraints
3/23/2013 Irvine, CA Save This JobAs a Product Engineer you will be a key team member responsible for new product development and product lifecycle management in collaboration with Marketing, Design, DFT, and Manufacturing teams for high-performance Tilera's manycore processors. As one of the primary product
5/9/2013 Santa Clara, CA Save This JobJob Description: Full cycle, ground up development and maintenance of automotive test and validation equipment, both hardware and software; Design and develop test equipment hardware/software to production standards, complying with all current regulatory and safety requirements;
4/22/2013 Fremont, CA Save This JobGeneral Description Responsible for design, layout, verification, and characterization of high-speed optical transceiver elements, TIAs, limiting amplifiers, I/Os, equalizers, high-speed CML, ring-oscillators, and other SerDes/CDR/PLL building blocks at data rates of 10Gb/s and
4/2/2013 Carlsbad, CA Save This JobThe successful candidate will be responsible for design of analog and mixed-signal circuits, meeting their architectural requirements and technical specifications. Depending on the level of responsibility, the candidate may also contribute to the architectural definition of these
3/23/2013 Sunnyvale, CA Save This JobThe successful candidate will be responsible for design of analog and mixed-signal circuits, meeting their architectural requirements and technical specifications. Depending on the level of responsibility, the candidate may also contribute to the architectural definition of these
3/23/2013 Sunnyvale, CA Save This Job