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Principal VLSI Design Engineer Jobs

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Principal DFT Engineer

eASIC

Title: Principal DFT Engineer Location: Santa Clara, CA, USA Job ID: 030117 Reports to: Director, Engineering Job Summary/Objective The Principal DFT Engineer will be responsible for DFT methodology in the Company test pattern generation including JTAG, boundary scan, memory

5/6/2017  Santa Clara, CA  Save This Job

Companies: Principal VLSI Design Engineer Jobs