RTL Design Engineer Jobs
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Principal ASIC Design Engineer
ClariPhy Communications
Job Description The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can include vector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs.
4/21/2013 Irvine, CA Save This JobSenior ASIC Design Engineer
SeaMicro
SeaMicro is looking for an experienced Senior ASIC Designer to architect and implement SeaMicro super-compute style fabric device for its next generation data center products. This is an excellent opportunity for high-energy candidates who can take a product from conception,
5/14/2013 Santa Clara, CA Save This JobDSP Datapath Design Engineer
Tensilica
Tracking Code 506 Job Description DSP Datapath Design Engineer ? 506 ? Santa Clara, CA Job Description: Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible
4/24/2013 Santa Clara, CA Save This JobASIC Logical Design Engineer
Uniquify, Inc.
Qualifications: Expertise in RTL design Experience in design verification Experience in system verilog PCI Express experience is a plus DDR experience is a plus BS or MS in electrical/computer engineering.
4/16/2013 Santa Clara, CA Save This JobPrincipal Physical Design Engineer
ClariPhy Communications
Job Description The engineer will be responsible for implementing tool flows and developing CAD methodologies generating flows & scripts. He/she will handle evaluation of tools in the development of new tool flows, and will also be responsible for managing related day to day
4/21/2013 Irvine, CA Save This JobSr. ASIC Design Engineer
Altierre
JOB DESCRIPTION: Experienced ASIC designer to design and develop digital components of wireless and display SOCs. Responsibilities include chip design / specification, FPGA prototyping, RTL coding, RTL verification, board bring up, and software integration/testing. The position
5/5/2013 San Jose, CA Save This JobSenior ASIC Design Engineer
Solarflare Communications
We are looking for ASIC design engineers to create industry leading next generation high speed network controller ASIC products. Responsibilities: Micro-architecture and RTL coding based on architecture specification Generate synthesis and timing signoff constraints
4/28/2013 Irvine, CA Save This JobSenior IC Design Engineer
Avalent Technologies
Required Skill and Experience: Resp. for logic & physical design of SoC for embedded, consumer, wireless & telecom applications. Job duties include RTL coding & simulation, Place & Route, Back-end physical design, design/timing verification utilizing Cadence & Synopsys tools.
4/27/2013 San Jose, CA Save This JobLogic Design Engineer
Tensilica
Tracking Code 514 Job Description As a member of the Logic Design Team for Xtensa processors you will be responsible for the micro-architecture development and specification of microprocessor cores, and their peripherals. You will design and implement the micro-architecture in
4/24/2013 Santa Clara, CA Save This JobQuality Engineer
Jasper Design Automation
Job Description / Responsibilities will include the following: Provide post sales support, including working closely with Field Application Engineers and R&D as needed. Performing QA activities including testing of new features and bug-fixes as it relates to fixes and
4/21/2013 Mountain View, CA Save This JobSenior Field Applications Engineer
Jasper Design Automation
Job Description / Responsibilities will include the following: 1. Acquire new and advanced formal concepts and apply advanced engineering methodologies to solve customer verification problems 2. Provide pre and post sales support, including working closely with account
4/21/2013 Mountain View, CA Save This JobStaff Engineer
Link_A_Media Devices
Staff Engineer, Santa Clara CA: Job Description: Responsible for design & implementation of register transfer level (RTL) coding for Flash Controller. Participate in block level micro architecture, write detailed specifications for various designs involving RTL
4/27/2013 San Jose, CA Save This JobEmulation Engineer
Calxeda, Inc.
Calxeda is headquartered in Austin, Texas. Our company mission is to bring revolutionary computational efficiency to the data center built around the ultra-low-power ARM architecture. Furthermore, we are developing server platform technologies that scale efficiently to thousands
5/10/2013 Austin, TX Save This JobSenior Field Applications Engineer
Atrenta
Job Details PROFILE OF THE CANDIDATE Atrenta is seeking a candidate with a minimum of 5+ years experience with RTL design and/or verification. The successful candidate will possess solid communication skills and ability to drive technical activities at customers. POSITION
4/16/2013 San Jose, CA Save This JobDesign Verification Engineer
VeriSilicon
Descriptions: 1. Develop environments for complex system functional verification. 2. Create and maintain RTL integration of system level components. 3. Write verification plans for system level IPs and systems. 4. Develop verification environments for IP and systems using
5/5/2013 Plano, TX Save This JobSTAFF ENGINEER (VLSI IMPLEMENTATION)
Audience
Job Details Responsibility is to design the next generation chips for audio noise suppression. This engineer would be responsible for Timing and physical design of our SoCs. Would involve close interactions with the VLSI Architecture, Design, Verification and Implementation
4/27/2013 Mountain View, CA Save This JobStaff/Sr Staff Software Engineer, Synthesis
Tabula
As a member of the Synthesis Development Team, participate in the development and support of Tabula?s industry leading synthesis engine for new programmable logic devices. The successful candidate will: Work cross-functionally with the field, software development and
5/20/2013 Santa Clara, CA Save This JobStaff Consulting Engineer
Atrenta
Job Details Job Description: Guide customers in the development of tool flows with Atrenta software tools and ensure they use the most optimum use model. Provide training for using Atrenta software tools and work with Product Development to address customer demands and make
5/16/2013 San Jose, CA Save This JobHardware Engineer - FPGA Verification
Palo Alto Networks
Description:We are looking for a self-motivated, team-oriented senior networking FPGA verification engineer to participate in the verification effort. This individual will be a key member of the FPGA system, full chip, and block level verification team. Responsibilities will
6/11/2013 Santa Clara, CA Save This JobSENIOR DFT ENGINEER
Audience
Job Details Responsibility is to design the next generation chips for audio noise suppression. This engineer would be responsible for DFT (Design For Testability) of our SoCs. Would involve close interactions with the VLSI Architecture, Design, Verification and Implementation
5/27/2013 Mountain View, CA Save This Job