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SeaMicro is looking for an experienced Senior ASIC Designer to architect and implement SeaMicro super-compute style fabric device for its next generation data center products. This is an excellent opportunity for high-energy candidates who can take a product from conception,4/9/2013 Santa Clara, CA Save This Job
We are looking for ASIC design engineers to create industry leading next generation high speed network controller ASIC products. Responsibilities: Micro-architecture and RTL coding based on architecture specification Generate synthesis and timing signoff constraints3/23/2013 Irvine, CA Save This Job
Job Description Your goal is to formulate and validate the next generation ASIC architecture for an audio noise suppression market leading product. You will work closely with VLSI Architecture, Design, Verification and DSP teams. Scope of responsibility will include proposing,3/23/2013 Mountain View, CA Save This Job
Candidate will be responsible for high speed ASIC design and verification for Network controller type ASICs. 10+ experience in the ASIC and design and verification methodology, with some experience in emulation platforms is a plus. Candidate must have working experience of OVM3/23/2013 Irvine, CA Save This Job
Job Description / Responsibilities will include the following: 1. Acquire new and advanced formal concepts and apply advanced engineering methodologies to solve customer verification problems 2. Provide pre and post sales support, including working closely with account4/21/2013 Mountain View, CA Save This Job
SeaMicro is looking for an experienced Senior Chip Integration Engineer to drive the physical implementation of our next generation super-compute style fabric ASIC. This is an excellent opportunity for high-energy candidates with strong technical leadership skills to take a chip4/9/2013 Santa Clara, CA Save This Job
Required Skill and Experience: MS/Ph.D. in Electrical Engineering with 5 years of ASIC design experience. A strong background in ASIC design process and development, Verilog, Synthesis, place and route, and verification. Previous management experience is3/19/2013 San Jose, CA Save This Job
Reporting to: Verification Manager, VLSI Engineering Location: Irvine, CA or Los Altos, CA Job Description The Design Verification team is growing and has need of a top talent, senior to principal level, ASIC functional verification engineer. Responsible for the development4/21/2013 Irvine, CA Save This Job
Responsibility: Work with Incentia Sales team on pre-sales and post-sales benchmark and customer supports for Taiwan or Asia territory. Develop product demo, application notes, and training materials, and help Sales team engage and close customer accounts. Requirement: BS, MS, or4/14/2013 Santa Clara, CA Save This Job