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VLSI Design & Backend Engineer Jobs

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Senior Principal, DSP ASIC Design Engineer

ClariPhy Communications

Reporting to: Director, VLSI Engineering Location: Irvine or Los Altos, CA Job Description The engineer will be responsible for low power design and implementation of advanced DSP (Digital Signal Processing) algorithms in high speed transceiver ASICs. Responsibilities include DSP

6/4/2015  Irvine, CA  Save This Job

Companies: VLSI Design & Backend Engineer Jobs