Analog Design Engineer Link_A_Media Devices
Experience of modeling hi-speed I/O's, PCB interconnects, and package with respect to parameters such as jitter, reflection, crosstalk, SSN and ground/power bounce.
Have strong timing and signal integrity background of DDR2/DDR3/Flash memory interface system.
Have strong knowledge of transmission lines and low-power termination schemes.
Capable to provide design guidelines to PCB layout and perform post route simulations for timing and signal quality.
Hands on DDR2/3 IO and associated control circuitry design experience with design tools including HSPICE and Cadence Spectre and familiar with physical layout and post-layout simulation.
Familiarity with IBIS model is a plus.
MSEE with 5+ years of experience in transistor level circuit design.
Familiar with lab equipment such as oscilloscope.
Excellent communication skills and ability to interface with other teams and customers in a dynamic start-up environment.
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Santa Clara, CA 95051