Analog Design, Principal Engineer / Manager / Sr. Manager Inphi
THIS JOB HAS EXPIRED We are looking for an Analog and Mixed-Signal Design Engineering Lead to contribute to the development of high-speed Phy layer SerDes centric ICs, including development of Receivers, Transmitters, PLLs, DLLs, as well as other parts of clock generation/distribution. The successful candidate must have a proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.
MSEE or PHD with minimum 10+ years of experience in deep sub-micron analog/mix-signal circuit design.
Experience of leading a minimum of 3-5 analog design engineers from architecture definition, implementation to lab evaluation and release to production for at least 2 projects.
High-speed and analog circuit design experience including one or more of the following: PLLs, DLLs, High-speed custom and I/O, SerDes, Clock and Data Recovery.
Deep sub-micron process design experience at 65nm or below.
A track record of developing high volume commercial products
Working knowledge of industry best practices.
Strong fundamentals in circuit theory, design, and layout
Creative design ability to solve problems demanding the highest levels of speed and power performance
Experienced in Cadence design flow
Strong communication and presentation skills
Ability to work independently as well as lead a team
Ability to work across functions and levels
||Santa Clara, CA |
THIS JOB HAS EXPIRED