ASIC Design Engineer (Processor/Cache/Memory) Magnum Semiconductor

Magnum is currently seeking an ASIC Design Engineer responsible for the design of our next generation compression products and SOCs. Tasks include micro-architecture, RTL design, synthesis, timing analysis and DFT.

Responsibilities:

Collaborate with architecture teams to develop efficient micro-architecture for a module
Contribute heavily to full chip integration and flow development to minimize design effort and time
Support physical design, board development and product engineering teams through tape-out, silicon qualification and high volume production


Requirements:

BSEE, MSEE preferred
7+ years in ASIC design - from concept through production
Strong micro-architecture experience for high speed and low power designs
Experienced in designing high performance processor / cache / memory controllers and familiarity with embedded CPUs
Experienced in chip level integration
Experienced in all aspects of ASIC flow - synthesis, timing, dft, power validation
Lab/bring-up experience is required
Strong written and verbal communication skills
Proficient in scripting languages (perl/python) desired
FPGA experience is also a plus.

Location:	591 Yosemite Drive Milpitas, CA 95035 United States