ASIC DESIGN ENGINEER Open-Silicon

Educational Requirement: BSEE or equivalent Relevant Experience: 3+ years experience in ASIC Design

Description: This position will be part of a small, fast-paced Design team utilizing leading-edge design tools and methodologies to enable the design of large, multi-million gate ASICs across a variety of domains. The Design Engineer is responsible for a wide variety of tasks including; architecture and design of subsystems based on device specifications, logic development using Verilog and System Verilog, and subsystem debugging through the development and use of directed test benches. The designer must be experienced in techniques utilized around asynchronously clocked boundaries and related design hazards. The position requires solid understanding of synthesis and timing closure constraint development around module I/O and clocking.

Requirements:

BSEE or equivalent experience
3+ years experience in IC (or advanced FPGA) design
Experience with Synopsys, Mentor, or Cadence based simulators
Experience with Synopsys or Cadence based synthesis and static timing closure
Excellent written and oral communication skills
Strong debugging skills
Strong scripting skills
Experience with formal verification tools, hardware design and debug, SystemC and other programming languages are a plus.
Knowledge of Object oriented verification frameworks; OVM, VMM, UVM is a plus
Experience working with Emulators, Accelerators and FPGA based prototyping a plus

Location:	Raleigh, NC United States