ASIC Design Engineers (multiple openings) Uniquify, Inc.
Following standard practices, implement and veridy deep sub-micron multi-million gate SoC (System on Chip) ASIC Designs. Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, developement, design and implementation of top/block level floor-plans; performance of clock-tree synthesis and high fan-out net synthesis; plan place and route architecture; conduct static timing analysis. Implement DRC, LVS and Antenna; determine the cause of any potential cause for gate array failure, ensuring parasitic extraction; and, perform design validation and provide formal verification.
Minumum Masters degree in Electrical Engineering or Bachelor's degree in plus five years of progressive experience in ASIC design.
||Santa Clara, CA |