Santa Clara Categories:
ASIC Verification/DFT Engineer Uniquify, Inc.
Candidate must have 3 to 5 years experience in simulation / verification of complex designs in verilog / system verilog. Experience in gate level timing simulation and DFT related experience is a plus. Qualifications:
Thorough understanding of verilog constructs and syntax is a must"
The last 2 to 3 years of experience should be focused on ASIC verification both at a functional block level and a system level.
Extremely well versed in verilog.
Working knowledge of C/C++
Additional working knowledge of System verilog and/or System C is desirable.
Well versed in scripting languages like Perl etc.
Demonstrated ability to write verification code and debug functional and system level issues by coordinating with individual designers and system architects.
| Location: | Santa Clara, CA United States |
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Uniquify, Inc.
Self FundedAll Jobs: at Uniquify, Inc.
| Web Site: | www.uniquify.com |
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| Headquarters: | 00000 United States |
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