ASIC VERIFICATION ENGINEER Open-Silicon
Relevant Experience: 3+ years? experience in ASIC Verification
Location: Raleigh, North Carolina
Description: This position will be part of a small, fast-paced Verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, multi-million gate ASICs. The Verification Engineer is responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques; designing verification components such as bus functional models, monitors, and behavioral models; implementing functional coverage and assertions using System Verilog; and developing test and functional coverage plans based on device specifications. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing functional coverage results.
BSEE or equivalent experience
3+ years experience in IC verification, including experience with constrained-random, coverage driven verification environments
Experience developing and working with object oriented verification languages (Vera, Specman, System Verilog, VMM, OVM, UVM)
A solid understanding of object-oriented concepts and experience designing class-based test benches
Excellent written and oral communication skills
Strong debugging skills
Strong C/C++, Perl, and scripting skills
Experience with formal verification tools, hardware design and debug, SystemC and other programming languages are a plus.
Experience working with OVM, or Specman e is a plus
Experience working with Emulators, Accelerators and FPGA based prototyping a plus
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