Design for Test Engineer - Manycore Processors Tilera
Tilera is growing! Check out the stand out silicon startup of Silicon Valley. This is a great time to work with a small team and make something big happen in processors. As a senior level DFT Engineer you will be a key team member responsible for developing and maintaining test vectors and ATE test programs for Tilera?s of high performance manycore processors. This includes test programs to be used for production, characterization, qualification, and debug of existing and upcoming products.
You will work with a number of teams, such as Design, DFT and Marketing, to ensure the test programs are of the highest quality and comprehensively test all aspects of the product?s datasheet with appropriate guard bands. As one of the primary product technical resources, you will work with our silicon manufacturer, suppliers, vendors, assembly/test houses, pro-actively driving product test, electrical characterization, datasheet creation, qualification, yield analysis/improvements, cost reduction programs, off-shore transfers, and customer quality issues.
Define and develop ATE programs for production, characterization, qualification and debug
Define and maintain Final Test and Sort Hardware, ATE load boards, ATC hand-test and handlers, test sockets and other test hardware
Work with Design engineering to develop, debug, and improve efficiency on structural and functional test patterns for ATE (JTAG, ATPG, Targeted Functional, Speed/Power)
Develop flows to fault grade functional and ATPG patterns to estimate overall test coverage
Work on initial test vector checkout and debug on ATE for new and existing products
Develop specifications for test program tagging and revision control, test program release procedures, test setup validation procedures, new test site bring-up and qualification
Work with Design, DFT, Test, and PE to collect, evaluate and process data needed for yield improvement, characterization, and qualification
Support production level testing at local and overseas test facilities
Help analyze customer returns; assist in identifying and resolving problems, developing new tests, and improving efficiency and effectiveness of existing tests
7 years minimum direct Semiconductor industry experience
BSEE, BSCE, or other equivalent degree
Good understanding of all aspects of ATE programming. Preferably Verigy 93K
Expertise with commercial scan insertion & ATPG tools from RTL to ATE required. Mentor Testkompress experience is a strong plus.
Solid knowledge of Verilog language and simulators, including Verilog-2001 and System Verilog extensions.
Experience developing and using Makefiles for flow automation
Strong in developing and maintaining scripts. Perl is OK; Python experience strongly preferred. Programming in both Perl and Python needed
Working knowledge of memory BIST flows, from RTL to ATE, is a plus.
C++ programming skills a plus.
||San Jose, CA |