Design Verification Engineer VeriSilicon
THIS JOB HAS EXPIRED Descriptions:
1. Develop environments for complex system functional verification.
2. Create and maintain RTL integration of system level components.
3. Write verification plans for system level IPs and systems.
4. Develop verification environments for IP and systems using C, verilog, Specman, SystemVerilog,
5. Contribute improvements to verification methodologies, and toolsets.
6. Develop RTL designs from specifications.
1. 3-8 years experiences.
2. BS EE a must/MS EE preferred.
3. Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux.
4. Great debugging and problem isolation skills.
5. AXI, AHB, APB interconnect.
6. Computer architecture, memory subsystems.
7. Implementing verification methodologies including constrained random verification, coverage
closure, Assertion Based Verification, Universal Verification Methodology
8. Implementing RTL logic designs.
||Plano, TX |
THIS JOB HAS EXPIRED