Design Verification Engineer SeaMicro
The role involves ASIC and FPGA verification including contributing to verification methodology, developing test plans that ensures high coverage between random, directed and in-system environments, system infrastructure development and debug, with significant focus on testing infrastructure development.
ASIC and FPGA verification in a System Verilog (OVM) and Verilog based environment
Architect and implement scalable, reusable test benches, fully inclusive of random environment, functional coverage, error generation, checkers and monitors, assertion methodology based on OVL or SVA
Tool creation, Gate Simulation, Coverage Analysis, integrating and testing standard IP models
System level contribution such as performance study, interaction with software, QA and architecture team.
Strong verification background and proven experience in architecting and implementing complex, reusable test benches
Proficiency in object oriented programming and data structures
Proficiency in Verilog and System Verilog (or other HVL) required. Programming skill and experience in one or more of C, C++ and perl is a strong plus. Comfort with a diversity of programming environments, tools and challenges
Experience with high speed serial interfaces (such as PCIe) or networking a strong plus
Experience with silicon bring up
Experience with industry standard methodologies such as OVM, VMM, aVM, eRM
Strong debug skills
Candidate will likely have MS in EE with 8 or more years of relevant experience
||Sunnyvale, CA |