Hardware Engineer - Chip Design Palo Alto Networks
We are looking for a FPGA or ASIC Design Engineer to be involved in a variety of projects. This position will require a good understanding in FPGA or ASIC development from concept / architecture level to final implementation and verification of final design.
- Full FGPA or ASIC design cycle involving architecture definition, RTL coding, simulation, timing analysis, synthesis, place & route and final verification.
- Implementations using Verilog
- System integration with board-level designs
- System-level Analysis and Architectural design
- Work with other engineers on a team to integrate FPGA or ASIC designs on projects that include hardware and software design components
- Experience in FPGA or ASIC design
- In-depth knowledge of Xilinx/Altera chips, design flows and lab bring-up flows
- Hands on experience using design and verification tools such as Synplicity, ISE/Quartus, VCS/Modelsim etc
- Experience working with full hardware design cycles from spec to production
- Experience in defining and managing complex high-speed digital architectures
- Experience working in security, telecommunications, networking, or related industries
- Experience in design and verification of interfaces such as Serdes, XGMII/RGMII, DRAM, SRAM, TCAM, host bus, etc.
- Independent and self-managing
- Strong communication skills (verbal and written)
- BS EE, CE or CS; or equivalent work experience required, MSEE preferred
||Santa Clara, CA |