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Hardware Engineer - Verification Palo Alto Networks
THIS JOB HAS EXPIRED
We are looking for a self-motivated, team-oriented senior networking hardware verification engineer to join the hardware verification team. This individual will be a key member of the hardware system, full chip, and block level verification team. Responsibilities will include developing the verification environment; developing test plans and verifying the function of the chip.
Day-to-Day Responsibilities:
- Responsibilities will include hands-on implementation work for every aspect of hardware verification, working closely with the system group, architects, RTL designers and verification teams
- Developing the verification flow and methodology, testbench and test cases, plus executing the test plan, working closely with the design team to ensure the highest design quality
- Debug test failures at block, full chip, and system level
- Evaluate and enhance test plans to increase test coverage
- Run regression
- The candidate also needs to have a full understanding of design using Verilog, and working experience with C/C++.
Desired Skills & Experience:
- BS EE, CE or CS; or equivalent work experience required, MSEE preferred
- Minimum of 5 years of hardware design verification experience with a proven track record of successfully verifying and delivering complex chips
- Experience in going through at least one complete and successful chip design/verification cycle from architecting and creation of chip test environment to tape-out and post-silicon validation is required.
- Strong communication/interpersonal skills required
Proven track record in the following areas of DV required:
- Test bench design and implementation
- Test plan definition
- Constrained random test development
- Coverage specification and analysis
- Reference model design and implementation
- Automation of the regression test suite
Solid technical skills in the area of design verification:
- Strong object-oriented software design and programming skills in C/C++, and at least one of the following: SystemVerilog, VMM, OVM, UVM is required. Experience with UVM is highly desirable
- Solid verification skills: planning, problem solving, debugging, random testing, adversarial testing required
- Experience in formal verification desired
- Networking experience is highly desirable
| Location: | Santa Clara, CA United States |
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THIS JOB HAS EXPIRED
Palo Alto Networks
Investors: Globespan Capital Partners, Greylock Partners, Sequoia CapitalAll Jobs: at Palo Alto Networks
| Web Site: | www.paloaltonetworks.com |
|---|---|
| Headquarters: | 2130 Gold Street Suite 200 Alviso, CA 95002 United States |
| Industry: | Software |
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