High Speed Protocol Staff Engineer/Technical Achronix Semiconductor
THIS JOB HAS EXPIRED Type of Position: Regular, Exempt
Reports to: Product Engineering Director
? Planning and execution of PCIe IP validation and characterization at the device and
? Drive validation and interoperability utilizing PCIE Exerciser and Analyzer Modules
? Development and Delivery of FPGA reference designs to accelerate customer adoption
and design win activity leveraging FPGA Architecture to demonstrate System Integration.
? Responsible for Achronix?s PCIe IP Infrastructure, Develop Technical notes, design
guidelines and interoperability testing and compliance reporting of PCIe Interfaces.
? Support Overall Product Bring Up of IP Interfaces and associated hard and soft IP in the
? Participation in next generation Product Definition evaluating Hard IP capabilities and
suitability for targeted applications.
? Strong working knowledge and experience in RTL logic design and simulation (Verilog
? Experience in IP verification and verification methodologies.
? Working knowledge of transceiver/SERDES architecture and FPGA design.
? Experience with timing analysis and timing closure specifically in an FPGA environment.
? Hands on experience in debugging Protocol Interfaces using Exerciser and Analyzer
Equipment, experience in lab automation a plus.
? Design/Validation experience in serial interface protocol PHY and MAC layers in PCI
Express. Experience in GigaEthernet, 10GE/40GE/100GE and Interlaken a plus.
? Strong in technical writing and communication (verbal) skills.
A minimum of 5 years performing the tasks outlined in Job Description / responsibilities section.
? MSEE preferred.
||333 West San Carlos Street |
San Jose, CA 95110
THIS JOB HAS EXPIRED