High Speed Protocol Validation Staff Engineer/Technical Lead Achronix Semiconductor
Type of Position: Regular, Exempt
Reports to: Product Engineering Director
? Validation of high speed protocol IPs such as PCIe, Ethernet or Interlaken at the device
and system level.
? Integration of protocol IPs in the FPGA design flow
? Development of FPGA reference designs to accelerate customer adoption and system
? Perform interoperability testing and generate compliance reports
? Creation of Application notes and design guidelines
? Support Overall Product Bring Up of IP Interfaces and associated hard and soft IP in the
? Participation in next generation Product Definition evaluating Hard IP capabilities and
suitability for targeted applications.
? Strong working knowledge and experience in RTL logic design and simulation (Verilog
? Experience in IP verification and verification methodologies.
? Design/Validation experience in serial interface protocol PHY and MAC layers in PCIe or
Ethernet or Interlaken.
? Hands on experience in debugging Protocol Interfaces using Exerciser and Analyzer
Equipment, experience in lab automation a plus.
? Experience with timing analysis and timing closure specifically in an FPGA environment.
? Working knowledge of transceiver/SERDES architecture and FPGA design.
? Strong in technical writing and communication (verbal) skills.
A minimum of 5 years performing the tasks outlined in Job Description / responsibilities section.
? MSEE preferred.
||San Jose, CA |