Santa Clara Categories:
IP Developer eASIC
Job ID: US2011011Qualifications:
Principle design engineer with MS in Electrical Engineering/Computer Engineering and at least 10+ years of design experience and has successfully delivered complex designs to production.
Job Summary:
You will be involved in design and verification of 1G 28G protocols including but not limited to PCIe Gen 3.0/2.0/1.0, Gigabit Ethernet, XAUI, CPRI, SRIO, 10G Base-R, Interlaken, etc. You will also need to perform frontend to backend tasks using semi-custom design flow including but not limited to design, floorplanning, verification, synthesis, timing closure, ECO, power analysis, etc. You will be involved in pre-silicon and post-silicon debug and support and you will work independently with local and global counterparts.
Description:
At least 5 years experience on digital protocol IP design for High Speed Serial protocols (such as PCI Express 2.0/2.1/3.0, Gigabit Ethernet, Interlaken, 10G Ethernet, CPRI, etc)
Experience must include architecture definition and IP development on Physical Coding Sublayer, Media Access Controller, Data Link and Transaction layer components
Experience in ASIC design methodology from front-end to back-end covering RTL Verilog/VHDL coding, Logic Verification (VMM/SystemVerilog is a plus), Synthesis, Floorplanning, Formal Verification, Static Timing Analysis. Experience in Place and Route is an added advantage
Provide Floorplaning Guidance & Review of critical layout designs
Work with our counterparts on many inter-dependent deliverables across geographical sites from various departments like Product Marketing, Test Development, Software Engineering, Product Engineering, Technology, Reliability, Applications, etc
Good communication and presentation in English is expected
Experience
BSEE/MSEE/PHD with minimum 10+ years of experience in high gate-count digital/mixed-signal IC design at 65nm or smaller technology with clock frequency > 400 MHz
Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment preferably for several products.
Strong language user in SystemVerilog, Verilog, Perl, Unix Shell
Experience in both RTL and gate level verification and debug
Experience in coverage based/random test environment and assertion generation
Experience in Cadence or Synopsys design environments, for example using NC-Verilog, RTL compiler, ETS is a plus
Design experience in 2 of following product areas
High speed serial link (PCI-E, SATA, 10G Ethernet, HDMI/Display Port, etc)
DDR2/DDR3 memory controller
High speed network or switching controller
PC chipset, North/South Bridge controller
Other multi-million gates digital/mix-signal design
Skills:
Define module level architecture specifications for next generation Mixed-Signal products
RTL code implementation using Verilog/SystemVerilog
Own pre-layout synthesis and timing closure using Cadence design environment
Work with backend engineer on post-layout timing closure
Work with verification engineering to debug test cases in RTL and Gate Level simulation environment. Define and generate assertion for his/her own module
Post-silicon debug and correlation.
| Location: | 2585 Augustine Drive Suite 100 Santa Clara, CA 95054 United States |
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eASIC
Investors: Crescendo Ventures, Kleiner Perkins Caufield & ByersAll Jobs: at eASIC
| Web Site: | www.easic.com |
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| Headquarters: | 2585 Augustine Drive Suite 100 Santa Clara, CA 95054 United States |
| Industry: | Semiconductors |
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