IP Development HW Leader eASIC
Job ID: US2011012
IP Development HW Leader
This position involves leading a team of HW IP developers in the creation of interface and logic fabric IP for eASIC structured ASIC devices. The position will involve active IP development as well as team leadership. Target markets are the communication and video sector with strong experience preferred in one of these target markets
Bachelors or Masters Degree
At least 5 years experience leading a team of people developing sophisticated IP (PCI Express Controllers, Interlaken MACs, VbyONETx/Rx, Ethernet MACs, DDR memory controllers for example) with proven successful field deployment.
At least 10 years experience developing IP for FPGAs, ASIC or Structured ASIC devices with proven success in field deployments.
excellent communication skills and leadership qualities
ability to successfully manage projects to a marketing requirements document and agreed upon schedule
knowledge of Verilog, UNIX scripting and C programming
Experience using one of the following simulation tools: VCS, Modelsim, Verilog XL
Demonstrable knowledge of successful testing strategies and testbench architectures
Strong knowledge of High speed transceiver technologies and proven experience developing IP using Transceivers.
Knowledge of IP limitations in relation to silicon I/O architecture and performance limitations
Willingness to work with teams in Europe and Malaysia.
||2585 Augustine Drive |
Santa Clara, CA 95054