Logic Design Engineer for a Multi Core Network Processor-Growth Opportunity NetLogic Microsystems

Description

Have you ever wanted to own your own block?

If so, you will have the opportunity in this group. You will initially be modeling, then architecting, designing and coding. We are looking for logic design engineers that have the drive to learn and challenge themselves on MIPS SoC products built on 40nm and beyond process technologies.

This is an excellent opportunity for someone who loves to take on challenges in Network Algorithms and convert them into hardware. You will have the opportunity to learn about and work on various SoC blocks like SRIO, PCIe, USB, SATA, compression/decompression, security and regular expression.

You will contribute to the advancement of Netlogic?s cutting-edge logic design methodology and to the continual improvement of critical methodology linkages to circuit, physical design, and design verification.

Responsibilites:

Covert high level specs or/and algorithms into hardware
Model, architect, design IO or/and accelerator blocks, and support it through the entire life cycle including verification, synthesis, placement & routing and timing closure.
Work effectively with design verification engineers to recommend and help develop verification and test strategies for various design blocks.
Work closely with circuit designers to merge logic and circuit techniques together to meet design objectives.

Requirements:

MSEE or BSEE with 3-5 years? experience in logic design.
Must be able to write RTL
Must have knowledge in interface protocols like PCIe, USB, SATA, SRIO and some exposure to Computer Architecture and Queuing Theory.
Knowledge of Verilog, multi-domain clock synchronization, pipelining, and low-power design techniques.
Knowledge of static timing analysis.
Working familiarity with various families of high performance circuit techniques and their tradeoffs

Location:	Santa Clara, CA United States