Manager, Physical Design Engineer ClariPhy Communications
THIS JOB HAS EXPIRED Reporting to: Director, Silicon Implementation
Location: Irvine, CA or Los Altos, CA
Candidates will be responsible for managing members of a physical design team, to enable
efficient layout work execution and ensure highest quality product results. In addition to
managing project execution, he/she will be overseeing implemention of tool flows and
developing CAD methodologies/generating layout flows & scripts. He/she must have strong
technical layout/timing closure skills. Responsibilities include managing evaluation of tools,
development of new tool flows, managing day to day layout, timing closure/backend activities,
meeting project schedules. He/she will also be required to be fluent in scripting languages such
as TCL and/or Unix shell languages. Other script languages such as awk, perl, and C are a plus.
Other responsibilities include the following layout design work:
? Full chip level floorplanning/prototyping, integration and layout
? Block level layout and timing closure
? Static Timing/Crosstalk Analysis and timing closure
? Synthesis/Physical Synthesis
? Power/IR/EM analysis
? Physical verification (LVS/DRC/ERC)
? ECO implementation
Required Skills & Experience
? Must have strong management/project management skills as well as outstanding technical
? Must have a minimum of 2 years of experience managing teams and project execution.
? Must understand chip layout/physical design concepts, methodologies and flows (i.e.
floorplanning, power planning, power/IR/EM analysis, custom routing, pad ring etc.)
? Must have an understanding of static timing and crosstalk/noise analysis and timing closure
concepts, methodologies and flows.
? Must have an understanding of RTL/gate synthesis concepts, methodologies and flows.
? Solid hands on experience with the following areas of design:
o Layout, place and route
o Static timing/crosstalk analysis
o RTL/gate synthesis
o Physical verification
o Power/IR/EM analysis
? Hands on experience with following layout CAD tools is a must:
o Layout: Aprisa, Talus, ICC OR FirstEncounter
o Synthesis: Design Compiler OR RTL Compiler
o Static timing: Primetime, Tekton, Goldtime
? Minimum 10 years of experience with BSEE or 7 years experience with MSEE
||16 Technology Drive |
Irvine, CA 92618
THIS JOB HAS EXPIRED