Manager, Verification Inphi
Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
Inphi is seeking a Manager/Principal verification engineer who will be responsible for leading a small verification team to refine the verification architecture, develop the test bench environment, generate verification plan and execute the test plan using SystemVerilog for next generation High Mixed-Signal and ASIC products. He/she is expected to be a hands-on leader and a domain expert in the functionality and application of the product in addition to the verification methodology. Non-technical responsibilities will include schedule & deliverable management and people management of team members. The candidate will work closely with the team of chip architects, digital engineers and analog mixed-signal design engineers.
Work with architects and designers and be the domain expert of the products
Work with project leaders and verification team to define the verification plan, staff the project and execute to the plan for quality design releases
Document and track verification status using coverage matrix and bug tracking system. Take action to ensure on time delivery of the project.
Refine verification architecture/methodology for future products
Maintain and support the existing verification environment
Hands-on technical leader working with the team to
Create/debug test cases for both RTL and Gate level verification
Define and generate assertions and functional coverage points
Automate verification environment using Perl and Shell Scrips
MSEE or PHD with minimum 10+ years of experience in multi-million gates of digital/mixed-signal design verification.
A proven verification manager/leader who had led the team went through the product development cycles multiple times.
Experience in building full chip test bench using UVM/OVM methodology
Experience in building test bench components from the design specification
Experience in using the 3rd party verification IPs
Experience in coverage based/random test environment and assertion generation
Experience in RTL and gate level verification and debugging pre and post silicon
Experience of silicon bring up and debug is a plus
Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.
Verification experience in some of following product area:
DDR2/DDR3/DDR4 memory controller
High speed network or switching controller
Flash Memory or SSD controller
SATA/PCI-E controller verification
SOC with embedded ARM processer
PC chipset, North/South Bridge controller
||Santa Clara, CA |