Memory Interface Staff Engineer/Technical Lead Achronix Semiconductor
THIS JOB HAS EXPIRED Job Description/Responsibilities
? Planning and execution of External Memory Interface characterization and system level
validation including blocks such as DLLs and GPIO. Support rates up to 2133 Mbps for
? Interact with design and software development groups in device level and board /system
validation and characterization.
? FPGA centric reference design development: Architecture, detailed design, coding, bring
up , testing , performance measurements/demonstration and delivery for Customers.
? Responsible for Achronix?s External Memory IP product development and support.
? Develop Technical notes, design guidelines, interoperability testing for DDR2/3 RLDRAM
II and QDR II External memory interfaces.
? Develop Technical notes, design guidelines, Interface Test Reports for various External
? Support Overall Product Bring Up of External memory Interface hardware and associated
hard and soft IP in the FPGA fabric.
? Participation in next generation External Memory Interface requirements definition and
? Knowledge and Familiarity with Memory Interfaces such as DDR2,DDR3,QDR II and
? Verilog / vhdl ? rtl coding / simulation and validation in FPGA based boards
? Hands on experience in debugging PCBs, using high end scopes compliance testing in a
hardware lab and experience in lab automation
? Strong in technical writing and communication (verbal) skills
? Knowledge of high speed serial protocols a plus
A minimum of 5 years performing the tasks outlined in Job Description / responsibilities section.
? MSEE preferred.
||Santa Clara, CA |
THIS JOB HAS EXPIRED