Next Generation Multi-Core Processor Design Engineer NetLogic Microsystems

Description

One chip- 20 CPUs, 80 threads and 100 Gbps networking. That is just part of NetLogic Microsystems aggressive multi-core processor roadmap now.

The merger with Broadcom is close at hand and we expect to gain even stronger market position with our multi-core processors, along with tremendous product synergy when the transition is complete.

Our goal is and will continue to be to develop leading edge processors at the top of the power and performance curve.

This is a fast moving, technically challenging opportunity for a mid-level microprocessor design engineer who wants to work in a small team environment and a chance to fully own major design blocks.

The successful candidate will be a hands-on CPU Logic Designer responsible for performing micro-architecture and logic design. He/She will work on advanced processor design areas such as Out-of-Order Instruction Scheduling and Execution, Multi-Threading, high performance cache subsystem etc.

The Processor Design Engineer will also contribute to the advancement of Netlogic?s cutting-edge logic design methodology and to the continual improvement of critical methodology linkages to circuit, physical design, and design verification.

This individual will work effectively with design verification engineers to recommend and help develop verification and test strategies for various design blocks, and will also work closely with circuit designers to merge logic and circuit techniques together to meet design objectives.
Requirements:

Must possess knowledge in the area of internal microprocessor logic design demonstrated by having worked on one or more of the MIPS, SPARC, X86, PowerPC, ARM based core-processor pipeline
Knowledge of Verilog, multi-domain clock synchronization, pipelining, and low-power design techniques.
Knowledge of static timing analysis.
Working familiarity with various families of high performance circuit techniques and their tradeoffs.
Must have 3-5 work experience in front-end chip design. Work experience with processor design is preferred but not required.

Location:	Santa Clara, CA United States