Principal ASIC Design Engineer ClariPhy Communications
The engineer will be responsible for optical PHY DSP (Digital Signal Processing) centric block modeling, RTL design/coding, DSP block (can include vector matching) verification, synthesis and static timing analysis of next generation optical networking ASICs. Typical activities include coding and verification of DSP block models (?C?, ?C++?, Matlab), RTL coding, writing verification plans and execution, synthesis, formal verification (LEC) and static timing analysis. Successful candidate will have working knowledge in DSP algorithms used in optical networking, OTN standards, DSP centric block design, hands on experience with matching DSP block model functionality to RTL?s, synthesis, static timing analysis and functional verification .
Required Skills & Experience
? Bachelor?s in Engineering or equivalent and at least 10 years of relevant experience is required.
? The successful candidate will be experienced with the IC/ASIC design/verification flow through at least three project cycles from concept through production release of silicon.
? Strong working knowledge in DSP algorithms used in optical PHYs (timing recovery, feed forward equalizers, carrier recovery, FEC etc.), modeling and model verification.
? Optical networking systems (in particular OTN standard) knowledge is mandatory.
? Hands on experience with matching DSP model functionality to RTL?s.
? Fluency with Verilog, System Verilog or VHDL. Strong knowledge in SystemC, ?C?, ?C++? or Matlab is compulsory.
? Experience in RTL debugging using conventional EDA tools like Cadence IES, Mentor Graphics Modelsim or Synopsys VCS.
? Experience in various hardware development tools like Synopsys Design Compiler, Primetime and Formality, or Cadence RTL Compiler and Conformal is compulsory.
? The engineer must have a well developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements.
? Good knowledge of scripting in tcl or Perl.
? Experience with low power design and verification flows highly desirable.
? Hands-on experience with synthesis, formal verification, static timing analysis, DFT (scan, JTAG, memory BIST) logic insertion.
||16 Technology Drive |
Irvine, CA 92618