Principal Engineer, Analog Design Inphi
Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
Inphi is seeking a principal digital design engineer who will be a technical individual contributor and responsible for development of high-speed serial and parallel I/Os, PLL/DLL, full chip clock generation and distribution for memory interface mixed-signal ICs. The candidate must have a proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production.
MSEE or PHD with minimum of 10+ years experience in deep sub-micron analog/mix-signal circuit design.
Experienced with guiding and mentoring analog design engineers from architecture definition, implementation to lab evaluation.
High-speed custom circuit and I/O development for DDR3/4 or GDDR4/5 applications or high-speed (10Gbps and above) mixed-signal and analog circuit design experience including one or more of the following: PLLs, DLLs, SerDes, Clock and Data Recovery, line drivers, equalizers
Deep sub-micron process design experience at 40nm or 28nm.
A track record of developing high volume commercial products
Working knowledge of industry best practices.
Experience of leading a 2-3 people team is a plus
Strong fundamentals in circuit theory, design, and layout
Creative design ability to solve problems demanding the highest levels of speed and power performance
Experienced in Cadence design flow
Strong communication and presentation skills
Ability to work independently as well as in teams
Ability to work across functions and levels
||Santa Clara, CA |