Principal Engineer, Analog & Mixed-Signal IC DesignInphi
MSEE or PHD with minimum 10+ years of experience in deep sub-micron analog/mix-signal circuit design.
Experience of leading 3-5 analog design engineers from architecture definition, implementation to lab evaluation and release to production for at least 2 projects.
High-speed and analog circuit design experience including one or more of the following: PLLs, DLLs, High-speed custom and I/O, SerDes, Clock and Data Recovery, DDRx/GDDRx Receiver or Driver.
Deep sub-micron process design experience at 65nm or below.
A track record of developing high volume commercial products
Working knowledge of industry best practices.
Strong fundamentals in circuit theory, design, and layout
Creative design ability to solve problems demanding the highest levels of speed and power performance
Experienced in Cadence design flow
Strong communication and presentation skills
Westlake Village, CA 91361