We are looking for analog and mixed-signal design engineers to contribute to the development of components for high-speed SerDes design and clock generation / distribution for SoC ICs. The candidate must have a proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.
MSEE or PHD with minimum 10+ years of experience in deep sub-micron analog/mix-signal circuit design.
Experienced with guiding and mentoring analog design engineers from architecture definition, implementation to lab evaluation.
High-speed (10Gb/.s and above) mixed-signal and analog circuit design experience including one or more of the following: PLLs, DLLs, High-speed custom I/O, SerDes, Clock and Data Recovery, line drivers, equalizers.
Deep sub-micron process design experience - 65nm and below.
A track record of developing high volume commercial products
Working knowledge of industry best practices.
Strong fundamentals in circuit theory, design, and layout
Creative design ability to solve problems demanding the highest levels of speed and power performance
Experienced in Cadence design flow
Strong communication and presentation skills
Ability to work independently as well as in teams
Ability to work across functions and levels
Westlake Village, CA 91361