Principal Engineer, Digital Design Inphi
Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
Inphi is seeking a principal digital design engineer who will be a technical individual contributor and responsible for defining module level architecture specifications, performing RTL design, synthesis, timing closure and verification for next generation Mixed-Signal/ASIC products. He/she will also contribute to the design methodology/flow in a digital/mixed-signal IC design environment. The candidate will work closely with the team of chip architects, project lead, design/verification engineers and analog mixed-signal design engineers.
Work with architects and project leaders to define/document the chip/module level micro-architecture specifications and be the domain expert of the products
Work with project leaders, design and verification team to define the verification plan
RTL design implementation using Verilog/SystemVerilog.
Own pre-layout synthesis and timing closure using Cadence design environment.
Work with backend engineer on post-layout timing closure.
Work with verification engineering to debug test cases in RTL and Gate simulation
Post-silicon debug and correlation.
MSEE/PHD with minimum 10+ years of experience of multi-million gates digital/mixed-signal IC design
Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
Experience in both RTL and gate level verification and debug
Experience of lower power design using CPF flow/methodology in 40nm or 28nm
Experience of DFT insertion and debug
Experience in coverage based/random test environment and assertion generation.
Experience in Cadence design environment using NC-Verilog, RTL compiler, ETS
Design experience in some of following product areas
High speed serial link (PCI-E, SATA, 10G Ethernet, HDMI/Display Port, etc)
DDR2/DDR3 memory controller.
High speed network or switching controller.
PC chipset, North/South Bridge controller.
Other multi-million gates digital/mix-signal design.
||Santa Clara, CA |