Principal Engineer / Manager, Digital Design Inphi
THIS JOB HAS EXPIRED Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
We are looking for a Principal Lead Digital Design Engineer who will be responsible for leading a smaller digital design team. Technical responsibilities range from defining top and module level architecture specifications, performing RTL design, synthesis, timing closure and verification for next generation Mixed-Signal products. The candidate is also expected to contribute to design methodology/flow in a digital/mixed-signal IC design environment. Non-technical responsibilities will include schedule & deliverable management and people management of team members. The candidate will work closely with the team of system architects, verification engineers and analog mixed-signal design engineers.
Technical leadership, digital chip and block level design management and leadership as well as people management.
Define chip level architecture specifications and lead the implementation for next generation Mixed-Signal, high speed phy layer products.
RTL code implementation using Verilog/SystemVerilog.
Own pre-layout synthesis and timing closure using Cadence design environment.
Work with backend engineer on post-layout timing closure.
Work with verification engineering to debug test cases in RTL and Gate Level simulation environment. Define and generate assertion.
Post-silicon debug and correlation.
BSEE/MSEE/PHD with minimum 12/10/8+ years of experience in multi-million gates digital/mixed-signal IC design at 65, 40nm or smaller technology.
Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
Been a technical leader responsible for a group of 3-5 engineers from micro architecture specification to silicon for at least 2 projects.
Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.
Experience in both RTL and gate level verification and debug.
Experience in coverage based/random test environment and assertion generation.
Experience in Cadence design environment using NC-Verilog, RTL compiler, ETS is a plus.
Design experience in some of following product areas
High speed serial link (PCI-E, SATA, 10G Ethernet, HDMI/Display Port, etc)
High speed network or switching controller.
DDR2/DDR3 memory controller.
PC chipset, North/South Bridge controller.
Other multi-million gates digital/mix-signal design.
||Westlake Village, CA |
THIS JOB HAS EXPIRED