Principal Engineer, Verification Inphi
Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
We are looking for a Lead / Principal Verification Engineer to lead verification of our next generation high speed mixed signal designs. The candidate must have proven record of verifying complex digital and/or mixed signal designs leading to successful field proven products. The candidate is also expected to contribute to verification methodology / flow in a digital/mixed-signal IC design environment. Non-technical responsibilities will include schedule & deliverable management from team members. The candidate will work closely with the team of system architects, digital design engineers and analog mixed-signal design engineers.
Technical leadership, own chip and block level verification.
Define chip level verification and lead / technically manage all verification activities for specific product, including schedule and deliverables.
Work with digital design engineering to debug test cases in RTL and Gate Level simulation environment.
Post-silicon debug and correlation.
BSEE/MSEE/PHD with minimum 12/10/8+ years of experience in verification of multi-million gates digital/mixed-signal IC designs.
2-3 years verification lead for multiple chips.
Experience in entire verification flow. From planning, testbench creation, RTL/gate level simulations to coverage and signoffs.
SystemVerilog (VMM, OVM or UVM). UVM preferred.
Scripting perl/python for flow support.
Experience in DSP/uControllers based designs.
Good Communication skills.
Highly Desired Experience / Skills:
Verification experience in some of following areas
High speed serial links (PCI-E, SATA, 10G Ethernet, HDMI/Display Port, etc).
High speed network or switching controller.
Knowledge/Prior experience in IEEE 802.3 related 100G PHYs.
Serdes, Equalization, ADC/DAC
Analog Modeling Experience.
Ultrasim mixed signal simulations.
||Santa Clara, CA |