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Principal Hardware Engineer Achronix Semiconductor
Job Description/Responsibilities Primary Responsibilities:
The employee will work on the design and implementation of full-custom, highperformance digital asynchronous circuits used in the next-generation Achronix FPGA
fabric. This work will be done in Intel?s advanced 22nm process technology. The
employee should be comfortable designing dynamic logic and dealing with issues such
as signal integrity, leakage, charge sharing, layout-dependent effects, and design-formanufacturing constraints. The employee will work closely with experienced mask
designers to floorplan and implement his or her design. Optimizing the circuits for area
and power will be important. The employee will work with other engineers in the team to
develop innovative asynchronous circuits optimized for performance, density, and
power-efficiency.
Secondary Responsibilities:
The employee will work with others in the team to design and maintain the unique
Achronix CAD flow for designing, verifying, and characterizing asynchronous circuits.
These duties will involve writing tools specifically used for developing asynchronous
circuits in 22nm, as well as writing scripts to interface with commercial CAD tools. The
employee will help develop tool flows to verify analog properties of circuits (charge
sharing, cross coupling, etc.).
The employee will evaluate characteristics of process geometries beyond 22nm and
help guide changes to design methodologies and product parameters at those
geometries. The employee will help conceive and assess circuit and architecture
innovations for near- and far-future Achronix products. The employee will be
responsible for documenting his or her work, especially how it integrates with other
pieces of the FPGA. The employee will work with the Achronix software team to ensure that the software used by Achronix?s customers correctly models the performance and
power consumption of the circuits that the employee has designed.
Skills:
? Employee should be comfortable with commercial CAD tools used for layout,
extraction, LVS, and simulation (digital and analog)
? Employee should have experience writing and verifying RTL (Verilog or VHDL)
? Employee should be capable in some scripting language (Perl, Python, Tcl, etc.)
and have experience writing scripts to interact with commercial CAD tools.
? Employee will work frequently with members of other teams on interfaces
between blocks of future Achronix products and hence should have excellent
oral and written communication skills and be able to cooperate and work in a
small group.
Experience / Education:
? Previous experience in a VLSI project in deep submicron
o Experience in 65nm, 45nm, 28nm, or beyond is a plus
o Should have experience working with full-custom dynamic logic
o Should have experience working with layout designers
o Should have experience working on high-performance logic
? No prior experience with asynchronous VLSI required
? Preferred: BS/MS + 10-15 years experience
| Location: | Santa Clara, CA United States |
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Achronix Semiconductor
Investors: Battery Ventures, Entrepia VenturesAll Jobs: at Achronix Semiconductor
| Web Site: | www.achronix.com |
|---|---|
| Headquarters: | 333 West San Carlos Street Suite 1050 San Jose, CA 95110 United States |
| Industry: | Semiconductors |
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