PRINCIPAL RTL ENGINEER SandForce, Inc.

Responsibilities:

- Handle all ASIC design tasks: micro-architecture, RTL coding, verification, synthesis, timing closure.



Requirements:

- Strong problem solving skills. Must be familiar with ASIC design flow. Must have experience with lab debug Person may be responsible for test plans, development of verification infrastructure, test benches and test cases for functional verification of the chip.
- 5-10 years experience in design/verification of complex multi-million gate ASICS. Experience with storage semiconductors is a plus.



Education:

- Minimum BSEE/BSCS. MSEE preferred. Knowledge of Tcl/Tk is desirable. Good written and oral communication skills.

Location:	Saratoga, CA United States