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Principle Analog Design Engineer Solarflare Communications
THIS JOB HAS EXPIRED
Responsibilities:Responsible for the design and verification of CMOS analog and mixed signal circuits at the transistor level Concentration will be on PLL and SerDes design
Develop analog cell specifications and architectures
Input schematics and run spice simulations
Present simulation results at design reviews
Develop and verify verilog-A/Verilog-D models of analog circuits
Simulate functionality of analog circuits using Verilog-D/verilog-A
Lab testing and debug
Requirements:
8+ years of direct hands-on design experience with high frequency PLL's (>1GHz VCO's)
Experience designing all portions of PLL's, bandgaps, linear voltage regulators, opamps
Experience designing Serdes including CDR's, CTLE and DFE circuits
Experience designing Inductors
Proficient with Verilog-D/Verilog-A
Experience with analog layout techniques and ability to work closely with layout team
Design experience with CMOS 40nm and/or 28nm technology
Experience with Cadence analog design and simulation tools a must, prefer Cadence version 6.1 experience
BSEE required, MSEE preferred
Preferred Skills:
Experience using Spiral Inductor software a plus
Experience designing I/O?s and high speed cml logic cells a plus
Experience designing PCI-E Gen3 and KR SerDes a plus
| Location: | 9501 Jeronimo Road Suite 250 Irvine, CA 92618 United States |
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THIS JOB HAS EXPIRED
Solarflare Communications
Investors: Accel Partners, Foundation Capital, Intel Capital, Miramar Venture Partners, Oak Investment PartnersAll Jobs: at Solarflare Communications
| Web Site: | www.solarflare.com |
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| Headquarters: | 9501 Jeronimo Road Suite 250 Irvine, CA 92618 United States |
| Industry: | Semiconductors |
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