San Jose Categories:
R&D Openings Atoptech
Candidates should have a minimum of 2 years in physical design, logical/physical synthesis,timing analysis, or other related fields and possess a BS/MS/Ph.D. in EE, CS, or relatedfields. New college graduate applicants are welcome.Preferred knowledge/experience in the following areas:
Placement - Quadratic/Linear wire length optimization algorithms,
Macro Placement, timing-driven placement
DRC and/or P/G Routing - Design Rules
Timing Analysis - Static/Incremental timing analysis algorithms, timing constraints
Timing/Power Optimization -
Timing closure techniques, familiar with static and incremental timing analysis
RC Extraction - Interconnect models, resistance/capacitance extraction,Table-Based approach
Infrastructure - Strong computer science background, Tcl/Tk, multi-threading
QoR/QA Management - Strong shell (tcl/perl) programming, Timing Closure issues,
self motivated and strong analytical skill
| Location: | San Jose, CA United States |
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| Full Time |
Atoptech
Investors: Acorn Campus VenturesAll Jobs: at Atoptech
| Web Site: | www.atoptech.com |
|---|---|
| Headquarters: | 3255-3 Scott Boulevard Suite 200 Santa Clara, CA 95054 United States |
| Industry: | Semiconductors |
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