R&D OPENINGS Atoptech
Candidates should have BS/MS/Ph.D. in EE, CS, or related fields.
Preferred knowledge/experience in the following areas:
Timing Optimization - logic synthesis, physical synthesis, timing/power optimization, incremental timing analysis.
Clock Tree synthesis - skew analysis, skew optimization, clock gating techniques, clock-mesh generation
Floorplanning/Chip-Assembly - pin-assignment, feedthru insertion, hierarchical data management
Placement - standard-cell placement, macro placement, datapath placement
||3255-3 Scott Boulevard |
Santa Clara, CA 95054