Senior Analog Design Engineer ClariPhy Communications

Job Description
The Company seeks a full-time Analog IC Design Engineer to join a team of seasoned mixed signal design engineers. Responsible for low-level design according to specifications established by senior members of the team. Support senior members by running simulations. Assist during silicon bring up in the lab. Design Analog to Digital Converter (A/D), Digital to Analog Converter (D/A), Phase Lock Loop (PLL) and Programmable GAin Amplifier (PGA) using Complementary Metal Oxide Semiconductor (CMOS) technology at or below 40 nm.
Required Skills & Experience
The candidate must have a proven track record in the design and layout of high performance, low power, high speed CMOS A/D and D/A converters, PLLs, PGA, and filters. This person must have released products to high volume production successfully. The candidate must have experience in advanced CMOS technologies such as 65nm and/or 40nm. The candidate must be capable of leading the development of a complete AFE module. Experience with 10G communication is a plus. The candidate will have 8+ years of experience.
Low power, high performance analog circuit design
Familiarity with Cadence environment
Self driven, result oriented individual capable of leading a team
MSEE required, Ph.D. degree in EE preferred.

Location:	16 Technology Drive Suite 165 Irvine, CA 92618 United States