Senior ASIC Design Engineer ClariPhy Communications

Job Description
The engineer will be responsible for the DFT implementation, design, coding, synthesis and static timing analysis of the next general optical networking ASICs. Typical activities include development of hardware block design specifications, RTL coding, synthesis, formal verification (LEC), static timing analysis and DFT logic insertion/verification. Successful candidate will be knowledgeable in contemporary verification methodology like UVM, VMM or OVM. The engineer will interface with the backend group for the physical implementation of these hardware blocks. He or she will also be expected to contribute to development of effective hardware design methodology.
Required Skills & Experience
Hands-on experience with DFT (scan, JTAG, memory BIST) logic insertion required
The successful candidate will be experienced with the IC/ASIC development flow through at least one but preferably several project cycles from concept through production release of silicon
Experience in various hardware development tools like Synopsys Design Compiler, Primetime and Formality, or Cadence RTL Compiler and Conformal
Fluency with Verilog or VHDL HDL (preferably Verilog)
The engineer must have a well developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements
Hands-on experience with synthesis, formal verification and STA flow set up
Good knowledge of scripting in tcl or Perl
Experience with low power design flows highly desirable
Bachelors in Engineering or equivalent required.

Location:	16 Technology Drive Suite 165 Irvine, CA 92618 United States