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Senior ASIC Design Engineer Solarflare Communications
We are looking for ASIC design engineers to create industry leading next generation high speed network controller ASIC products.Responsibilities:
Micro-architecture and RTL coding based on architecture specification
Generate synthesis and timing signoff constraints
Take the design through synthesis and timing closure
Validate design in the lab
Lead and participate in technical design reviews
Requirements:
Minimum 10 years experience in ASIC design, implementation and methodology
Minimum 5 years experience in synthesis and timing closure of sub 90nm designs
Minimum 3 years experience validating the design in the lab
Familiar with physical design, formal verification and DFT implementation of 10 million+ gate designs
Verilog HDL design coding
SystemVerilog
C/C++ programming
OVM verification methodology
Perl scripting is a plus
Worked on at least two projects from Architecture definition to tape-out
Background in networking and bus protocols such as Ethernet, TCP-IP and PCIE protocols
Excellent oral and written communication skills
High energy, self driven and desire to constantly learn
BS in Electrical Engineering, Computer Science or Computer Engineering. MS in Electrical Engineering, Computer Science or Computer Engineering is highly recommended.
| Location: | 9501 Jeronimo Road Suite 250 Irvine, CA 92618 United States |
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Solarflare Communications
Investors: Accel Partners, Foundation Capital, Intel Capital, Miramar Venture Partners, Oak Investment PartnersAll Jobs: at Solarflare Communications
| Web Site: | www.solarflare.com |
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| Headquarters: | 9501 Jeronimo Road Suite 250 Irvine, CA 92618 United States |
| Industry: | Semiconductors |
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