Senior ASIC Design Engineers Link_A_Media Devices
Job Description and Requirements:
The qualified design applicant would be responsible for all aspects of the design activities, including architecture definition, design specification, design flow development, logic design and verification, timing closure, test vector generation, etc. for new generation SSD (Solid State Drive) controller ICs.
Familiarity with digital signal processing, SAS, SATA, PCIe, DDR is a plus.
System level / chip level experience is a big plus
SSD, Flash controller, Nand management IC design experience is desirable
Experience with FPGA emulation and hardware validation is desirable.
Being through iterations of design cycles including production is desirable
Are expected to have hands-on experiences in all aspects of RTL design flow from specification/architecture definition to design and verification.
Strong abilities in HDL design and modeling language is a must.
VCS, NCverilog, Formality, DCT, RTL-compiler, PrimeTime etc. is strongly desirable
ECC experience is a plus.
MS with 5 years or BS with 7 years in ASIC design is expected.
Background in verification methodologies including random and coverage driven verification is a plus.
Stable work history and excellent track record required
||2550 Walsh Avenue |
Santa Clara, CA 95051