Senior ASIC Engineer Avalent Technologies
Required Skill and Experience:
MS/Ph.D. in Electrical Engineering with 5 years of ASIC design experience. A strong background in ASIC design process and development, Verilog, Synthesis, place and route, and verification. Previous management experience is preferred.
Compose and lead a team in ASIC design for embedded CPU.
||405 River Oaks Parkway |
San Jose, CA 95134
|Employment Type:||Full Time|