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Senior ASIC Engineer Avalent Technologies
Required Skill and Experience:MS/Ph.D. in Electrical Engineering with 5 years of ASIC design experience. A strong background in ASIC design process and development, Verilog, Synthesis, place and route, and verification. Previous management experience is preferred.
Responsibilities:
Compose and lead a team in ASIC design for embedded CPU.
| Location: | 405 River Oaks Parkway San Jose, CA 95134 United States |
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| Full Time |
Avalent Technologies
Investors: Sycamore VenturesAll Jobs: at Avalent Technologies
| Web Site: | www.avalent.com |
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| Headquarters: | 405 River Oaks Parkway San Jose, CA 95134 United States |
| Industry: | Semiconductors |
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