Senior Design Engineer #2017 NetLogic Microsystems

Description

Job description: Design a functional unit in the cutting edge, high performance network processor. Develop the micro-architecture specification and implement RTL code for the involved blocks including integrating related IP. Evaluate and provide feedback for IP selection. Assist verification team in developing appropriate testbench, testplan and tests. Assist physical/circuit team for implementation. Assist systems team for board design & debug. Required experience must be in RTL & digital logic design. Exposure to computer architecture and high speed digital circuit design is required. Knowledge of the following is required: Verilog; Synopsys; Timing analysis; Multi-clock domain synchronization; System Verilog assertions; and scripting.



Requirements: Master?s degree or foreign equivalent in Electrical Engineering or related field + 3 years of experience, or equivalent-. -Equivalent is Bachelor?s degree or foreign equivalent in Electrical Engineering or related field + 5 years of experience.

Location:	Santa Clara, CA United States