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Senior Design Verification Engineer - 437 Tensilica
THIS JOB HAS EXPIRED
RESPONSIBILITIES:As a member of the Design and Verification Team you will be responsible for the verification of processor, DSP cores and processor based sub-system products
You will be responsible for the verification specification and the test plan for complex sub-system products
You will be responsible for System C model Processor integration into System Verilog testbench, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals
REQUIREMENTS:
Experience in system level validation
Experience in definition and building of constrained random based verification environment
Experience in delivering realistic and complete verification plan including functional and performance validation goals.
Good knowledge of computer architecture, processor, DSP and sub-system micro-architecture concepts
Proficient in advanced verification techniques such as random based stimuli generation, formal assertion and function coverage
Excellent analytical and debugging skills
Good working knowledge of Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies and System C modeling
Good experience in scripting languages like Perl, Unix shell or similar languages
Plus to have random instruction diagnostic generations for processors
Excellent written and oral communication skills are necessary
MS in EE /Computer Engineering with 7+ years of relevant experience or BS in EE/Computer Engineering with 10+ years of relevant experience.
| Location: | 3255-6 Scott Boulevard Santa Clara, CA 95054 United States |
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THIS JOB HAS EXPIRED
Tensilica
Investors: Foundation Capital, Oak Investment Partners, Windspeed VenturesAll Jobs: at Tensilica
| Web Site: | www.tensilica.com |
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| Headquarters: | 3255-6 Scott Boulevard Santa Clara, CA 95054 United States |
| Industry: | Software |
