Senior Full Chip Intergration Engineer - Multi-Core Processors NetLogic Microsystems

Description
We are looking for competitive, energetic people to help us build advanced communication chips to handle the traffic of tomorrow?s mobile internet. As a Fullchip Integration Engineer, you will be part of the database assembly and signoff for fabrication. You will have hands on experience with all aspects of VLSI design, methodology, and validation on leading edge superscalar, out-of-order, multi-core Systems-on-Chip. Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, NetLogic has a very challenging position open for those VLSI engineers seeking high growth opportunities.

Responsibilities:

Understand abstract circuit concepts and constraints, and implement design methodologies and validation requirements based on them
Be the expert in using the tools to do physical design and own the physical design flow development through various tapeouts.
Perform power, clock, and timing analysis on Fullchip databases
Assemble floorplans and design bus/switch/ring dataflows across an SoC
Everything else necessary to support physical design, low power design, timing analysis and closure, noise analysis and closure, parasitic extraction, backend power grid analysis, clock analysis, signal EM, DFM, circuit characterization, library modeling.

Requirements:

BSEE, MSEE Preferred
7+ years directly related to physical design expertise in state of the art ICs with emphasis on VLSI physical design and methodology exposure on 45 nm process nodes and below.
Hands on experience in Fullchip assembly
Excellent Software Skills with fluency in Perl and TCL, proficiency and/or ability-to-learn php, python, sql, Java, C/C++, html, xhtml
Power user of place and route tools such as Atoptech, ICC, Magma Talus or Cadence SOCe with experience in hierarchical flows.
Expertise with high performance, low power synthesis, STA, extraction, clock and power design and physical verification
Leadership experience in microprocessor tapeouts is desirable
Experience in bringing up new tools/methodologies to increase productivity and to enhance QoR
Ability to work in an energetic but small team environment.
Self motivator with excellent problem solving skills.

Location:	Santa Clara, CA United States