Senior IC Design Engineer Avalent Technologies
Required Skill and Experience:
Resp. for logic & physical design of SoC for embedded, consumer, wireless & telecom applications. Job duties include RTL coding & simulation, Place & Route, Back-end physical design, design/timing verification utilizing Cadence & Synopsys tools. Req. MSEE .
Individual will lead a small group of logic and circuit designer on a full custom embedded processor project. The individual will be responsible for designing the embedded processor to meet aggressive schedule and technical goals.
||405 River Oaks Parkway |
San Jose, CA 95134
|Employment Type:||Full Time|