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Senior IC Design Engineer Avalent Technologies
Required Skill and Experience:Resp. for logic & physical design of SoC for embedded, consumer, wireless & telecom applications. Job duties include RTL coding & simulation, Place & Route, Back-end physical design, design/timing verification utilizing Cadence & Synopsys tools. Req. MSEE .
Responsibilities:
Individual will lead a small group of logic and circuit designer on a full custom embedded processor project. The individual will be responsible for designing the embedded processor to meet aggressive schedule and technical goals.
| Location: | 405 River Oaks Parkway San Jose, CA 95134 United States |
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| Full Time |
Avalent Technologies
Investors: Sycamore VenturesAll Jobs: at Avalent Technologies
| Web Site: | www.avalent.com |
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| Headquarters: | 405 River Oaks Parkway San Jose, CA 95134 United States |
| Industry: | Semiconductors |
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