Senior Layout Design Engineer Solarflare Communications
Generate full custom layout of CMOS analog, transistor level circuits such as PLL's, Bandgaps, ADC's, DAC's, and Serdes circuits.
Responsible for DRC/LVS clean layout generation.
Experience using Cadence version 6.1 Virtuoso layout and Mentor Graphics Calibre DRC/LVS tools
Experience generating analog layouts in TSMC 40nm and/or 28nm process technologies
Experience with DFM rules, dummy metal, poly and OD insertion
Proficient in running DRC/LVS and resolving DRC/LVS issues
In-depth experience with analog layout and matching techniques
Experience generating Flip-Chip layouts and use of DNW
Experience with top level cell layout
10+ years of layout experience
Layout experience with ESD rules, I/O?s, high speed logic cells, standard cell logic cells and serdes a plus
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