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Senior Level R&D Engineers Altos Design Automation
Requirements:Ph.D EE or MS EE plus 1+ years experience (4+ for Senior positions) of C++ and STL. Candidates should have good communication skills and be willing to work independently. We prefer candidates with experience in:
SPICE
Transistor level circuit analysis
Standard cell, memory, IP characterization
IC variation modeling
Semiconductor process characterization
| Location: | 4020 Moorpark Avenue Suite 100 San Jose, CA 95117 United States |
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Altos Design Automation
Investors: Vista VenturesAll Jobs: at Altos Design Automation
| Web Site: | www.altos-da.com |
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| Headquarters: | 4020 Moorpark Avenue Suite 100 San Jose, CA 95117 United States |
| Industry: | Software |
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